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MC74AC175 MC74ACT175 Quad D Flip Flop With Master Reset
The MC74AC/ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops, when MR is low. The MC74AC/ACT175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input's state is transferred to the corresponding flip-flop's output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The MC74AC/ACT175 is useful for applications where the Clock and Master Reset are common to all storage elements. * Outputs Source/Sink 24 mA * ACT175 Has TTL Compatible Inputs QUAD D FLIP-FLOP WITH MASTER RESET
N SUFFIX CASE 648-08 PLASTIC
Pinout: 16-Lead Packages (Top View)
VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 D SUFFIX CASE 751B-05 PLASTIC Data Inputs Clock Pulse Input Master Reset Input Outputs Outputs
PIN NAMES
D0 - D3 CP MR Q0 - Q3 Q0 - Q3 1 MR 2 Q0 3 Q0 4 D0 5 D1 6 Q1 7 Q1 8 GND
LOGIC SYMBOL TRUTH TABLE
Inputs MR CP D Outputs Qn Qn D0 CP D1 D2 D3
L H H H
X
L
X H L X
L H L Qn
H L H Qn
MR Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition of Clock
FACT DATA 5-1
MC74AC175 MC74ACT175
LOGIC DIAGRAM
MR CP D3 D2 D1 D0
D
Q
D
Q
D
Q
D
Q
CP Q CD
CP Q CD
CP Q CD
CP Q CD
Q3 Q3
Q2 Q2
Q1 Q1
Q0 Q0
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
MAXIMUM RATINGS*
Symbol VCC Vin Vout Iin Iout ICC Tstg Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC VCC or GND Current per Output Pin Storage Temperature Value -0.5 to +7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 50 50 -65 to +150 Unit V V V mA mA mA C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout Supply Voltage DC Input Voltage, Output Voltage (Ref. to GND) VCC @ 3.0 V tr, tf Input Rise and Fall Time (Note 1) AC Devices except Schmitt Inputs VCC @ 4.5 V VCC @ 5.5 V tr, tf TJ TA IOH IOL Input Rise and Fall Time (Note 2) ACT Devices except Schmitt Inputs Junction Temperature (PDIP) Operating Ambient Temperature Range Output Current -- HIGH Output Current -- LOW -40 25 VCC @ 4.5 V VCC @ 5.5 V Parameter AC ACT Min 2.0 4.5 0 150 40 25 10 ns/V 8.0 140 85 -24 24 C C mA mA ns/V Typ 5.0 5.0 Min 6.0 5.5 VCC V Unit V
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
FACT DATA 5-2
MC74AC175 MC74ACT175
DC CHARACTERISTICS
74AC Symbol Parameter VCC (V) TA = +25C Typ VIH Minimum High Level Input Voltage 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum Low Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN IOLD IOHD ICC Maximum Input Leakage Current Minimum Dynamic Output Current Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 8.0 0.002 0.001 0.001 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 74AC TA = -40C to +85C Unit Conditions
Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 75 -75 80 V VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = - 50 A V *VIN = VIL or VIH - 12 mA IOH - 24 mA - 24 mA IOUT = 50 A V *VIN = VIL or VIH 12 mA IOH 24 mA 24 mA VI = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND
VIL
Maximum Low Level Input Voltage
V
VOH
Minimum High Level Output Voltage
V
V
A mA mA A
* All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
AC CHARACTERISTICS
74AC Symbol Parameter VCC* (V) Min fmax tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CP to Qn or Qn Propagation Delay CP to Qn or Qn Propagation Delay MR to Qn Propagation Delay MR to Qn 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 149 187 2.0 1.5 2.5 1.5 3.0 2.0 3.0 2.0 12.0 9.0 13.0 9.5 12.5 9.0 11.0 8.5 TA = +25C CL = 50 pF Typ Max 74AC TA = -40C to +85C CL = 50 pF Min 139 187 2.0 1.0 2.0 1.5 2.5 1.5 2.5 1.5 13.5 9.5 14.5 10.5 13.5 10.0 12.5 9.0 Max MHz ns ns ns ns 3-3 3-6 3-6 3-6 3-6 Unit Fig. No.
FACT DATA 5-3
MC74AC175 MC74ACT175
AC OPERATING REQUIREMENTS
74AC Symbol Parameter VCC* (V) Typ ts th tw tw trec Set-up Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP MR Pulse Width Low CP Pulse Width Recovery TIme MR to CP 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 TA = +25C CL = 50 pF 74AC TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum 4.5 3.0 1.0 1.0 4.5 3.5 4.5 3.5 0 0 4.5 3.0 1.0 1.0 4.5 3.5 5.0 3.5 0 0 ns ns ns ns ns 3-9 3-9 3-6 3-6 3-6
* Voltage Range 3.3 V is 3.3 V 0.3 V. Voltage Range 5.0 V is 5.0 V 0.5 V.
DC CHARACTERISTICS
74ACT Symbol Parameter VCC (V) TA = +25C Typ VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Additional Max. ICC/Input Minimum Dynamic Output Current Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 8.0 0.6 0.001 0.001 1.5 1.5 1.5 1.5 4.49 5.49 74ACT TA = -40C to +85C Unit Conditions
Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 -75 80 V V V VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = - 50 A *VIN = VIL or VIH - 24 mA IOH - 24 mA IOUT = 50 A *VIN = VIL or VIH 24 mA IOH 24 mA VI = VCC, GND VI = VCC - 2.1 V VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND
V
V
V
A mA mA mA A
* All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time.
FACT DATA 5-4
MC74AC175 MC74ACT175
AC CHARACTERISTICS
74ACT Symbol Parameter VCC* (V) Min fmax tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn Propagation Delay MR to Qn or Qn 5.0 5.0 5.0 5.0 175 2.0 2.0 2.0 10.0 11.0 9.5 TA = +25C CL = 50 pF Typ Max 74ACT TA = -40C to +85C CL = 50 pF Min 145 1.5 1.5 1.5 11.0 12.0 10.5 Max MHz ns ns ns 3-3 3-6 3-6 3-6 Unit Fig. No.
* Voltage Range 5.0 V is 5.0 V 0.5 V.
AC OPERATING REQUIREMENTS
74ACT Symbol Parameter VCC* (V) Typ ts (H) (L) th tw tw trec Set-up Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP MR Pulse Width, LOW CP Pulse Width, HIGH or LOW Recovery TIme MR to CP 5.0 5.0 5.0 5.0 5.0 TA = +25C CL = 50 pF 74ACT TA = -40C to +85C CL = 50 pF Unit Fig. No.
Guaranteed Minimum 2.0 2.5 1.0 3.0 3.0 0 2.0 2.5 1.0 4.0 3.5 0 ns ns ns ns ns 3-9 3-9 3-6 3-6 3-6
* Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Symbol CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Value Typ 4.5 45.0 Unit pF pF Test Conditions VCC = 5.0 V VCC = 5.0 V
FACT DATA 5-5
MC74AC175 MC74ACT175
OUTLINE DIMENSIONS
N SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
9
-A-
16
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
-A-
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
9
16
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
FACT DATA 5-6
*MC74AC175/D*
MC74AC175/D

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